ELEC3607: Embedded Systems (2013 - Semester 1)
|Unit:||ELEC3607: Embedded Systems (6 CP)|
|Faculty/School:||School of Electrical and Information Engineering|
A/Prof Leong, Philip
|Session options:||Semester 1|
|Versions for this Unit:|
|Site(s) for this Unit:||
|Pre-Requisites:||ELEC1601 AND ELEC2602.|
|Brief Handbook Description:||The aim of this unit of study is to teach students about microprocessors and their use. This includes architecture, programming and interfacing of microcomputers, peripheral devices and chips, data acquisition, device monitoring and control and communications.|
|Assumed Knowledge:||ELEC1601 AND ELEC2602. Logic operations, theorems and Boolean algebra, data representation, number operations (binary, hex, integers and floating point), combinational logic analysis and synthesis, sequential logic, registers, counters, bus systems, state machines, simple CAD tools for logic design, basic computer organisation, the CPU, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks.|
|T&L Activities:||Laboratory: Laboratory exercises to re-enforce theory.
Independent Study: Prelab exercises and reading of text.
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
|Attribute Development Method||Attribute Developed|
|Laboratory exercises consist of design and problem solving.||Design (Level 3)|
|Expertise specific to microcomputers and digital systems.||Engineering/IT Specialisation (Level 3)|
|Development of fundamentals of microcomputers and projects.||Maths/Science Methods and Tools (Level 3)|
|Skill in accessing and handling information on microcomputers.||Information Seeking (Level 2)|
|Working in groups to solve design problems.||Communication (Level 3)|
|Development of professional practice in design projects.||Professional Conduct (Level 1)|
|Working in teams on design projects.||Project Management and Teamwork (Level 2)|
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.Design (Level 3)
Final Exam: 2 hour exam.
Log Book: Log book kept on each laboratory exercise.
Assignment: Complete the design and implementation of an embedded system of the students` choosing.
|Faculty Policies & Procedures:||Academic Honesty in Coursework. All students must submit a cover sheet for all assessment work that declares that the work is original and not plagiarised from the work of others.
Coursework assessment and examination policy. The faculty policy is to use standards based assessment for units where grades are returned and criteria based assessment for Pass/Fail only units. Norm referenced assessment will only be used in exceptional circumstances and its use will need to be justified to the Undergraduate Studies Committee. Special consideration for illness or misadventure may be considered when an assessment component is severely affected. This policy gives the details of the information that is required to be submitted along with the appropriate procedures and forms.
Special Arrangements for Examination and Assessment. In exceptional circumstances alternate arrangements for exams or assessment can be made. However concessions for outside work arrangements, holidays and travel, sporting and entertainment events will not normally be given.
Student Appeals against Academic Decisions. Students have the right to appeal any academic decision made by a school or the faculty. The appeal must follow the appropriate procedure so that a fair hearing is obtained.
Note that policies regarding assessment submission, penalties and assessment feedback depend upon the individual unit of study. Details of these policies, where applicable, will be found above with other assessment details in this unit outline.
All university policies can be found at http://sydney.edu.au/policy
Various request forms for the Faculty of Engineering and IT can be found at http://sydney.edu.au/engineering/forms/
Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.
|Online Course Content:||http://www.eelab.usyd.edu.au/ELEC3607/index.html|
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
|Week 2||Independent study.|
|ARM Assembly language I.|
|Laboratory exercise 1: General Purpose I/O.|
|Week 3||Laboratory exercise 2: Switch Debouncing and General Purpose I/O.|
|ARM Assembly language II.|
|Week 4||Laboratory exercise 3: Counter/Timer.|
|CPU Interfaces I.|
|Week 5||Laboratory exercise 4: UART and Interrupts.|
|CPU Interfaces II.|
|Week 6||Laboratory exercise 5: Power Supplies.|
|Power Supplies and Oscillators I.|
|Week 7||Assignment 1.|
|Power Supplies and Oscillators II.|
|Week 8||Independent study.|
|Week 9||Case Study: Variometer I.|
|Week 10||Case study: Variometer II.|
|Week 11||Revision: Interrupts I.|
|Week 12||Revision: Interrupts II.|
|Assessment Due: Assignment|
|STUVAC (Week 14)||Independent study.|
|Exam Period||Final exam.|
|Assessment Due: Final Exam|
The following is a list of courses which have added this Unit to their structure.
This unit contributes to the achievement of the following course goals:
|Design (Level 3)||Yes||5.5%|
|Engineering/IT Specialisation (Level 3)||Yes||62%|
|Maths/Science Methods and Tools (Level 3)||Yes||21.5%|
|Information Seeking (Level 2)||Yes||0%|
|Communication (Level 3)||Yes||4.5%|
|Professional Conduct (Level 1)||Yes||0%|
|Project Management and Teamwork (Level 2)||Yes||6.5%|
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.