ELEC2004: Electrical Engineering: Foundations (2013 - Semester 1)
| Unit: | ELEC2004: Electrical Engineering: Foundations (6 CP) |
| Mode: | Normal-Day |
| On Offer: | Yes |
| Level: | Intermediate |
| Faculty/School: | School of Electrical and Information Engineering |
| Unit Coordinator/s: |
Dr Sathiakumar, Swamidoss
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| Session options: | Semester 1 |
| Versions for this Unit: | |
| Site(s) for this Unit: |
http://www.eelab.usyd.edu.au/ELEC2004 |
| Campus: | Camperdown/Darlington |
| Pre-Requisites: | None. |
| Prohibitions: | ELEC1103. |
| Brief Handbook Description: | The Three block Structure of the course: 1. Introduction to Electric Circuits: current and voltage, power, Kirchhoff’s Laws, sources and resistors, Ohm’s Law, series and parallel connections, voltage and current dividers, equivalent circuits. Inductors and capacitors, RC circuits, RL circuits, introduction to RLC circuits. 2. Electric Power Systems: sinusoidal signals, effective (rms) value of sinusoids, power in ac circuits, transformer principles and ideal transformers, balanced 3-phase circuits. Electromechanical machine types, DC machines, introduction to ac and induction machines. 3. Basic Electronics: Op amp, inverting amplifier, noninverting amplifier, basic op-amp circuits. Digital signals and circuits, truth table and basic logic functions, Boolean function, digital circuit design and realisation. Introduction to Sequential digital systems. |
| Assumed Knowledge: | None. |
| Additional Notes: | Lecture notes and course web site http://www.eelab.usyd.edu.au/ELEC2004 |
| Lecturer/s: |
Dr Sathiakumar, Swamidoss
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| Timetable: | ELEC2004 Timetable | |||||||||||||||||||||||||
| Time Commitment: |
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| T&L Activities: | Tutorial: Tutorials Laboratory: Laboratories E-Learning: Self paced elearning |
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
| Attribute Development Method | Attribute Developed |
| In tutorials and lab waorks several design task applied | Design (Level 3) |
| Basic knowledge and skills in electrical engineering are enforced | Engineering/IT Specialisation (Level 2) |
| Course material and labs provide students these fundamentals | Maths/Science Methods and Tools (Level 3) |
| Professional skills practiced and enhanced in laboratory and tutorial works. Teamwork in labs and encouraged in tutorials |
Professional Conduct (Level 3) |
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.
Design (Level 3)| Assessment Methods: |
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| Assessment Description: |
Log Book: Group work; Laboratory Notebook and report. Assignment: Tutorial Assignments Final Exam: Final Examination Mid-Sem Exam: Mid-Sem Exam 1 Mid-Sem Exam: Mid-Sem Exam 2 |
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| Grading: |
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| Faculty Policies & Procedures: | Academic Honesty in Coursework. All students must submit a cover sheet for all assessment work that declares that the work is original and not plagiarised from the work of others. Coursework assessment and examination policy. The faculty policy is to use standards based assessment for units where grades are returned and criteria based assessment for Pass/Fail only units. Norm referenced assessment will only be used in exceptional circumstances and its use will need to be justified to the Undergraduate Studies Committee. Special consideration for illness or misadventure may be considered when an assessment component is severely affected. This policy gives the details of the information that is required to be submitted along with the appropriate procedures and forms. Special Arrangements for Examination and Assessment. In exceptional circumstances alternate arrangements for exams or assessment can be made. However concessions for outside work arrangements, holidays and travel, sporting and entertainment events will not normally be given. Student Appeals against Academic Decisions. Students have the right to appeal any academic decision made by a school or the faculty. The appeal must follow the appropriate procedure so that a fair hearing is obtained. Note that policies regarding assessment submission, penalties and assessment feedback depend upon the individual unit of study. Details of these policies, where applicable, will be found above with other assessment details in this unit outline. All university policies can be found at http://sydney.edu.au/policy Various request forms for the Faculty of Engineering and IT can be found at http://sydney.edu.au/engineering/forms/ |
| Prescribed Text/s: |
Note: Students are expected to have a personal copy of all books listed.
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| Recommended Reference/s: |
Note: References are provided for guidance purposes only. Students are advised to consult these books in the university library. Purchase is not required.
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| Online Course Content: | http://www.eelab.usyd.edu.au/ELEC2004 |
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
| Week | Description |
| Week 1 | Introduction, units, quantities & measurements, Kirchhoff Current Law, Kirchhoff Voltage Law, energy flow, resistive circuits |
| Week 2 | Series and parallel connections |
| Week 3 | Thevenin’s equivalent, Source transformation |
| Assessment Due: Log Book | |
| Assessment Due: Tutorial Assignment | |
| Week 4 | Inductors and Capacitors |
| Week 5 | First order circuit, Sinusoids |
| Assessment Due: Mid-Sem Exam | |
| Week 6 | Power in AC circuits |
| Week 7 | Transformer Principles Introduction to 3-phase circuits |
| Week 8 | Source Delta connection and Y connection |
| Week 9 | Motors |
| Week 10 | Introduction to Op amps |
| Assessment Due: Mid-Sem Exam | |
| Week 11 | Linear Op-amp circuits (Buffer, Summing cct, Integrator) |
| Week 12 | Introduction to digital signals |
| Week 13 | Design and realisation of logic functions Introduction to microprocessors |
| Exam Period | Assessment Due: Final Exam |
Course Relations
The following is a list of courses which have added this Unit to their structure.
Course Goals
This unit contributes to the achievement of the following course goals:
| Attribute | Practiced | Assessed |
| Design (Level 3) | Yes | 47.5% |
| Engineering/IT Specialisation (Level 2) | Yes | 23.75% |
| Maths/Science Methods and Tools (Level 3) | Yes | 23.75% |
| Professional Conduct (Level 3) | Yes | 0% |
| Project Management and Teamwork (Level 3) | No | 5% |
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.
