ELEC1601: Introduction to Computer Systems (2013 - Semester 2)
|Unit:||ELEC1601: Introduction to Computer Systems (6 CP)|
|Faculty/School:||School of Electrical and Information Engineering|
|Session options:||Semester 2|
|Versions for this Unit:|
|Site(s) for this Unit:|
|Brief Handbook Description:||This unit of study introduces the fundamental digital concepts upon which the design and operation of modern digital computers are based. A prime aim of the unit is to develop a professional view of, and a capacity for inquiry into, the field of computing.
Topics covered include: data representation, basic computer organisation, the CPU, elementary gates and logic, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks.
|Assumed Knowledge:||HSC Mathematics extension 1 or 2|
|T&L Activities:||Project Work - in class: Design, build and test a project working in a team.
Independent Study: Preparation for tutorials, labs and project
Laboratory: Hands on lab work on computer systems, digital hardware and MIPS Assembler programming
Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.
|Attribute Development Method||Attribute Developed|
|Design software in a team project environment||Design (Level 1)|
|Detailed study of computer system fundamentals||Maths/Science Methods and Tools (Level 2)|
|Writing of assignments and reports. Oral presentation of project outcomes.||Communication (Level 2)|
|Team based laboratories with individual and group assessment components including oral examinations.||Professional Conduct (Level 1)|
|The team project assignment introduces students to teamwork and project management in an engineering context||Project Management and Teamwork (Level 2)|
For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.
Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.Design (Level 1)
Quiz: Quiz 1 - students will, under exam conditions, complete quizzes testing their knowledge of any material previously covered in lectures, tutorials and labs.
Final Exam: End of semester exam
Report: Assignment 1 Initial report. Students are required to have analysed the overall problem and present an initial design and project plan for solving it.
Report: Team project - Detailed Design. This is a group assignment, due in week 7. Each group must present a final design, indicating how each member will contribute to the project. At this stage, groups must also submit a draft acceptance test report, outlining the tests that the finished project is intended to be able to pass at the final demonstration. At this stage, groups must also submit a draft acceptance test report, outlining the tests that the finished project is intended to be able to pass at the final demonstration.
Project: Team project demonstration and design walkthrough. This is a group assessment, due in the laboratory in week 12. For the demonstration, groups must make a presentation to the tutor, showing how their design addresses the problem. Presentations must be accompanied by a poster. Groups must demonstrate their prototype to the tutor in the laboratory. The design must be shown to operate successfully several times. Students are expected to be able to intelligently answer questions about design and implementation choices made by the group.
Assignment: Assignment 4 Evaluation report. After the completion of the assignment, students are expected to reflect on their own contribution to the assignment, and evaluate the progress of their group.
Quiz: Quiz 2
Lab Skills: Three labs over 9 sessions
|Assessment Feedback:||Assessment feedback will be provided face to face in the labs and tutes, and via BlackBoard for assignments submitted online|
|Faculty Policies & Procedures:||Academic Honesty in Coursework. All students must submit a cover sheet for all assessment work that declares that the work is original and not plagiarised from the work of others.
Coursework assessment and examination policy. The faculty policy is to use standards based assessment for units where grades are returned and criteria based assessment for Pass/Fail only units. Norm referenced assessment will only be used in exceptional circumstances and its use will need to be justified to the Undergraduate Studies Committee. Special consideration for illness or misadventure may be considered when an assessment component is severely affected. This policy gives the details of the information that is required to be submitted along with the appropriate procedures and forms.
Special Arrangements for Examination and Assessment. In exceptional circumstances alternate arrangements for exams or assessment can be made. However concessions for outside work arrangements, holidays and travel, sporting and entertainment events will not normally be given.
Student Appeals against Academic Decisions. Students have the right to appeal any academic decision made by a school or the faculty. The appeal must follow the appropriate procedure so that a fair hearing is obtained.
Note that policies regarding assessment submission, penalties and assessment feedback depend upon the individual unit of study. Details of these policies, where applicable, will be found above with other assessment details in this unit outline.
All university policies can be found at http://sydney.edu.au/policy
Various request forms for the Faculty of Engineering and IT can be found at http://sydney.edu.au/engineering/forms/
Note: Students are expected to have a personal copy of all books listed.
|Online Course Content:||Notes and discussions will be provided on BlackBoard.|
|Note on Resources:||ELEC1601 Course Notes. Purchase at Copy Shop|
Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp
|Week 1||Introduction and overview|
|Week 2||Data representation|
|Week 3||Digital logic|
|Week 4||Architecture of a simple computer|
|Week 5||Instruction Set Architectures|
|Assessment Due: Report|
|Week 6||Computer Memory|
|Assessment Due: Quiz|
|Week 7||Computer Memory|
|Week 8||Input/Output and Storage|
|Assessment Due: Report|
|Week 9||System software|
|Week 10||Alternative Architectures|
|Week 11||Performance Measurement|
|Week 12||Network Organisation|
|Assessment Due: Quiz|
|Assessment Due: Project|
|Assessment Due: Assignment|
|Exam Period||Final exam|
|Assessment Due: Final Exam|
The following is a list of courses which have added this Unit to their structure.
This unit contributes to the achievement of the following course goals:
|Design (Level 1)||Yes||3%|
|Engineering/IT Specialisation (Level 2)||No||0%|
|Maths/Science Methods and Tools (Level 2)||Yes||76.49%|
|Information Seeking (Level 2)||No||0%|
|Communication (Level 2)||Yes||5%|
|Professional Conduct (Level 1)||Yes||3%|
|Project Management and Teamwork (Level 2)||Yes||12.5%|
These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.