ELEC1601: Introduction to Computer Systems (2013 - Semester 2)

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Unit: ELEC1601: Introduction to Computer Systems (6 CP)
Mode: Normal-Day
On Offer: Yes
Level: Junior
Faculty/School: School of Electrical and Information Engineering
Unit Coordinator/s: Pardo, Abelardo
Session options: Semester 2
Versions for this Unit:
Site(s) for this Unit:
Campus: Camperdown/Darlington
Pre-Requisites: None.
Brief Handbook Description: This unit of study introduces the fundamental digital concepts upon which the design and operation of modern digital computers are based. A prime aim of the unit is to develop a professional view of, and a capacity for inquiry into, the field of computing.

Topics covered include: data representation, basic computer organisation, the CPU, elementary gates and logic, peripheral devices, software organisation, machine language, assembly language, operating systems, data communications and computer networks.
Assumed Knowledge: HSC Mathematics extension 1 or 2
Lecturer/s: Pardo, Abelardo
Timetable: ELEC1601 Timetable
Time Commitment:
# Activity Name Hours per Week Sessions per Week Weeks per Semester
1 Lecture 2.00 2 13
2 Project Work - in class 1.00 1 8
3 Independent Study 3.00
4 Laboratory 2.00 1 10
T&L Activities: Project Work - in class: Design, build and test a project working in a team.

Independent Study: Preparation for tutorials, labs and project

Laboratory: Hands on lab work on computer systems, digital hardware and MIPS Assembler programming

Attributes listed here represent the key course goals (see Course Map tab) designated for this unit. The list below describes how these attributes are developed through practice in the unit. See Learning Outcomes and Assessment tabs for details of how these attributes are assessed.

Attribute Development Method Attribute Developed
Design software in a team project environment Design (Level 1)
Detailed study of computer system fundamentals Maths/Science Methods and Tools (Level 2)
Writing of assignments and reports. Oral presentation of project outcomes. Communication (Level 2)
Team based laboratories with individual and group assessment components including oral examinations. Professional Conduct (Level 1)
The team project assignment introduces students to teamwork and project management in an engineering context Project Management and Teamwork (Level 2)

For explanation of attributes and levels see Engineering & IT Graduate Outcomes Table.

Learning outcomes are the key abilities and knowledge that will be assessed in this unit. They are listed according to the course goal supported by each. See Assessment Tab for details how each outcome is assessed.

Design (Level 1)
1. Ability to apply concept, principles and techniques to configure a basic system.
2. Ability to scope, build and test an engineering artefact.
3. Proficiency in applying computer engineering knowledge in the design, construction and testing of commensurate solutions for specific engineering problems.
Maths/Science Methods and Tools (Level 2)
4. Ability to demonstrate understanding of the concepts and principles of computer architecture, digital logic design and microprocessor assembly language.
5. Ability to demonstrate understanding of the concepts, principles and relationship for computers, the internet and clients and servers.
6. Ability to demonstrate fundamental knowledge of computer engineering issues.
Communication (Level 2)
7. Ability to write reports to present design specific information and results concisely and accurately.
Professional Conduct (Level 1)
8. An appreciation of the professional practice, standards and responsibilities in working with hardware and software to the limit afforded by lab sessions and exercises.
Project Management and Teamwork (Level 2)
9. Ability to engage in team-based design, drawing on the knowledge, skills and creative talent of all members to deliver a solution to a particular engineering problem.
Assessment Methods:
# Name Group Weight Due Week Outcomes
1 Report No 5.00 Week 5 6, 7,
2 Quiz No 4.00 Week 6 4,
3 Report Yes 5.00 Week 8 7, 9,
4 Quiz No 4.00 Week 12 5,
5 Project Yes 5.00 Week 12 9,
6 Assignment Yes 5.00 Week 13 9,
7 Final Exam No 60.00 Exam Period 4, 5, 6,
8 Lab Skills No 12.00 Multiple Weeks 1, 4, 6, 8,
Assessment Description: Quiz: Quiz 1 - students will, under exam conditions, complete quizzes testing their knowledge of any material previously covered in lectures, tutorials and labs.

Final Exam: End of semester exam

Report: Assignment 1 Initial report. Students are required to have analysed the overall problem and present an initial design and project plan for solving it.

Report: Team project - Detailed Design. This is a group assignment, due in week 7. Each group must present a final design, indicating how each member will contribute to the project. At this stage, groups must also submit a draft acceptance test report, outlining the tests that the finished project is intended to be able to pass at the final demonstration. At this stage, groups must also submit a draft acceptance test report, outlining the tests that the finished project is intended to be able to pass at the final demonstration.

Project: Team project demonstration and design walkthrough. This is a group assessment, due in the laboratory in week 12. For the demonstration, groups must make a presentation to the tutor, showing how their design addresses the problem. Presentations must be accompanied by a poster. Groups must demonstrate their prototype to the tutor in the laboratory. The design must be shown to operate successfully several times. Students are expected to be able to intelligently answer questions about design and implementation choices made by the group.

Assignment: Assignment 4 Evaluation report. After the completion of the assignment, students are expected to reflect on their own contribution to the assignment, and evaluate the progress of their group.

Quiz: Quiz 2

Lab Skills: Three labs over 9 sessions
Assessment Feedback: Assessment feedback will be provided face to face in the labs and tutes, and via BlackBoard for assignments submitted online
Grading:
Grade Type Description
Standards Based Assessment Final grades in this unit are awarded at levels of HD (High Distinction), D (Distinction), CR (Credit), P (Pass) and F (Fail) as defined by Academic Board Resolutions: Assessment and Examination of Coursework. Details of Academic Board Resolutions are available on the University`s Policy website at http://www.usyd.edu.au/ab/policies/Assess_Exam_Coursework.pdf Standards for grades in individual assessment tasks and the summative method for obtaining a final mark in the unit will be set out in a marking guide supplied by the unit coordinator.
Special Conditions to Pass UoS In order to pass this unit, a student will be required to achieve at least 50% overall as well as at least 40% in the written examination and at least 40% for the total of the other components of assessment.
Faculty Policies & Procedures: Academic Honesty in Coursework. All students must submit a cover sheet for all assessment work that declares that the work is original and not plagiarised from the work of others.

Coursework assessment and examination policy. The faculty policy is to use standards based assessment for units where grades are returned and criteria based assessment for Pass/Fail only units. Norm referenced assessment will only be used in exceptional circumstances and its use will need to be justified to the Undergraduate Studies Committee. Special consideration for illness or misadventure may be considered when an assessment component is severely affected. This policy gives the details of the information that is required to be submitted along with the appropriate procedures and forms.

Special Arrangements for Examination and Assessment. In exceptional circumstances alternate arrangements for exams or assessment can be made. However concessions for outside work arrangements, holidays and travel, sporting and entertainment events will not normally be given.

Student Appeals against Academic Decisions. Students have the right to appeal any academic decision made by a school or the faculty. The appeal must follow the appropriate procedure so that a fair hearing is obtained.

Note that policies regarding assessment submission, penalties and assessment feedback depend upon the individual unit of study. Details of these policies, where applicable, will be found above with other assessment details in this unit outline.

All university policies can be found at http://sydney.edu.au/policy

Various request forms for the Faculty of Engineering and IT can be found at http://sydney.edu.au/engineering/forms/
Prescribed Text/s: Note: Students are expected to have a personal copy of all books listed.
Online Course Content: Notes and discussions will be provided on BlackBoard.
Note on Resources: ELEC1601 Course Notes. Purchase at Copy Shop

Note that the "Weeks" referred to in this Schedule are those of the official university semester calendar https://web.timetable.usyd.edu.au/calendar.jsp

Week Description
Week 1 Introduction and overview
Week 2 Data representation
Week 3 Digital logic
Week 4 Architecture of a simple computer
Week 5 Instruction Set Architectures
Assessment Due: Report
Week 6 Computer Memory
Assessment Due: Quiz
Week 7 Computer Memory
Week 8 Input/Output and Storage
Assessment Due: Report
Week 9 System software
Week 10 Alternative Architectures
Week 11 Performance Measurement
Week 12 Network Organisation
Assessment Due: Quiz
Assessment Due: Project
Week 13 Review
Assessment Due: Assignment
Exam Period Final exam
Assessment Due: Final Exam

Course Relations

The following is a list of courses which have added this Unit to their structure.

Course Year(s) Offered
Bachelor of Computer Science and Technology (Computer Science) 2009, 2010, 2011, 2012, 2013
Bachelor of Computer Science and Technology (Computer Science)(Advanced) 2013
Bachelor of Computer Science and Technology (Information Systems) 2013, 2010, 2011, 2012
Bachelor of Computer Science and Technology (Information Systems)(Advanced) 2013
Biomedical - Electrical Major 2013
Computer Engineering 2010
Computer Engineering/Commerce 2010
Electrical 2010, 2011, 2012, 2013
Electrical Engineering/Arts 2011, 2012, 2013
Electrical Engineering/Commerce 2010, 2011, 2012, 2013
Electrical (Bioelectronics) 2011, 2012
Electrical (Bioelectronics) Engineering/Arts 2011, 2012
Electrical (Bioelectronics) Engineering/Commerce 2011, 2012
Electrical (Bioelectronics) Engineering/Medical Science 2011, 2012
Electrical (Bioelectronics) Engineering/Science 2011, 2012
Electrical (Bioelectronics) Engineering/Law 2011, 2012
Electrical Engineering/Medical Science 2011, 2012, 2013
Electrical Engineering/Project Management 2012, 2013
Electrical Engineering/Science 2011, 2012, 2013
Electrical (Computer) 2011, 2012, 2013
Electrical (Computer) Engineering/Arts 2011, 2012, 2013
Electrical (Computer) Engineering/Commerce 2011, 2012, 2013
Electrical (Computer) Engineering/Medical Science 2011, 2013
Electrical (Computer) Engineering/Science 2011, 2012, 2013
Electrical (Computer) Engineering/Law 2011, 2012, 2013
Electrical (Power) 2010, 2011, 2012, 2013
Electrical (Power) Engineering/Arts 2011, 2012, 2013
Electrical (Power) Engineering/Commerce 2010, 2011, 2012, 2013
Electrical (Power) Engineering/Medical Science 2011, 2012, 2013
Electrical (Power) Engineering/Science 2011, 2012, 2013
Electrical (Power) Engineering/Law 2010, 2011, 2012, 2013
Electrical (Telecommunications) 2011, 2012, 2013
Electrical (Telecommunications) Engineering/Arts 2011, 2012, 2013
Electrical (Telecommunications) Engineering/Commerce 2011, 2012, 2013
Electrical (Telecommunications)/Medical Science 2011, 2012, 2013
Electrical (Telecommunications) Engineering/Science 2011, 2012, 2013
Electrical (Telecommunications) Engineering/Law 2011, 2012, 2013
Electrical (Power) Engineering/Project Management 2012, 2013
Software 2010, 2011, 2012, 2013
Software Engineering/Arts 2011, 2012, 2013
Software Engineering/Commerce 2010, 2011, 2012, 2013
Software Engineering/Medical Science 2011, 2012, 2013
Software Engineering/Project Management 2012, 2013
Software Engineering/Science 2011, 2012, 2013
Telecommunications 2010
Bachelor of Information Technology (Computer Science) 2009, 2010, 2011, 2012, 2013
Information Technology(Computer Science)/Bachelor of Arts 2012, 2013
Information Technology(Computer Science)/Bachelor of Commerce 2012, 2013
Information Technology (Computer Science)/Medical Science 2012, 2013
Information Technology(Computer Science)/Bachelor of Science 2012, 2013
Bachelor of Information Technology (Information Systems) 2010, 2013, 2012
Information Technology(Information Systems)/Bachelor of Arts 2013
Information Technology(Information Systems)/Bachelor of Commerce 2013
Information Technology(Information Systems)/Bachelor of Science 2013
Flexible First Year (Stream B)/Medical Science 2012, 2013

Course Goals

This unit contributes to the achievement of the following course goals:

Attribute Practiced Assessed
Design (Level 1) Yes 3%
Engineering/IT Specialisation (Level 2) No 0%
Maths/Science Methods and Tools (Level 2) Yes 76.49%
Information Seeking (Level 2) No 0%
Communication (Level 2) Yes 5%
Professional Conduct (Level 1) Yes 3%
Project Management and Teamwork (Level 2) Yes 12.5%

These goals are selected from Engineering & IT Graduate Outcomes Table which defines overall goals for courses where this unit is primarily offered. See Engineering & IT Graduate Outcomes Table for details of the attributes and levels to be developed in the course as a whole. Percentage figures alongside each course goal provide a rough indication of their relative weighting in assessment for this unit. Note that not all goals are necessarily part of assessment. Some may be more about practice activity. See Learning outcomes for details of what is assessed in relation to each goal and Assessment for details of how the outcome is assessed. See Attributes for details of practice provided for each goal.